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PDU1032H
5-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU1032H)
FEATURES
* * * * *
GND
data 3 (R) delay devices, inc.
PACKAGES
32 31 GND OUT
Digitally programmable in 32 delay steps Monotonic delay-versus-address variation Precise and stable delays Input & outputs fully 10KH-ECL interfaced & buffered Fits 32-pin DIP socket
1 2
ENB
A0 VEE GND IN
7 8 9 11
26 25 24
A1 A2 GND
N/C N/C OUT GND ENB N/C N/C N/C GND ENB N/C IN
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
N/C N/C A2 A1 VEE A0 N/C N/C A4 VEE A3 N/C
PDU1032H-xxC4 SMD PDU1032H-xxMC4 Mil SMD PDU1032H-xx DIP PDU1032H-xxM Mil DIP
A3 VEE
15 16
17
A4
FUNCTIONAL DESCRIPTION
The PDU1032H-series device is a 5-bit digitally programmable delay line. The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on the address code (A4-A0) according to the following formula:
PIN DESCRIPTIONS
IN Signal Input OUT Signal Output A0-A4 Address Bits ENB Output Enable VEE -5 Volts TDA = TD0 + TINC * A GND Ground where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 0.5ns through 20ns, inclusively. The enable pin (ENB) is held LOW during normal operation. When this signal is brought HIGH, OUT is forced into a LOW state. The address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
* * * * * * * * Total programmed delay tolerance: 5% or 2ns, whichever is greater Inherent delay (TD0): 5.5ns typical for dash numbers up to 5, greater for larger #'s Setup time and propagation delay: Address to input setup (TAIS): 3.6ns Disable to output delay (TDISO): 1.7ns typical Operating temperature: 0 to 70 C Temperature coefficient: 100PPM/C (excludes TD0) Supply voltage VEE: -5VDC 5% Power Dissipation: 615mw typical (no load) Minimum pulse width: 20% of total delay
DASH NUMBER SPECIFICATIONS
Part Number PDU1032H-.5 PDU1032H-1 PDU1032H-2 PDU1032H-3 PDU1032H-4 PDU1032H-5 PDU1032H-6 PDU1032H-8 PDU1032H-10 PDU1032H-12 PDU1032H-15 PDU1032H-20 Incremental Delay Per Step (ns) 0.5 0.3 1.0 0.5 2.0 0.5 3.0 1.0 4.0 1.0 5.0 1.0 6.0 1.0 8.0 1.0 10.0 1.5 12.0 1.5 15.0 1.5 20.0 2.0 Total Delay (ns) 15.5 2.0 31 2.0 62 3.1 93 4.6 124 6.2 155 7.8 186 9.3 248 12.4 310 15.5 372 18.6 465 23.2 620 31.0
NOTE: Any dash number between .5 and 20 not shown is also available. (c)1997 Data Delay Devices
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DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU1032H
APPLICATION NOTES
ADDRESS UPDATE
The PDU1032H is a memory device. As such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. The timing restrictions are shown in Figure 1. After the last signal edge to be delayed has appeared on the OUT pin, a minimum time, TOAX, is required before the address lines can change. This time is given by the following relation: TOAX = max { (Ai - A i-1) * TINC , 0 } where A i-1 and Ai are the old and new address codes, respectively. Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required TOAX has elapsed. A similar situation occurs when using the ENB signal to disable the output while IN is active. In this case, the unit must be held in the disabled state until the device is able to "clear" itself. This is achieved by holding the ENB signal high and the IN signal low for a time given by: TDISH = Ai * TINC Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required TDISH has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input pulse width and period listed in the AC Characteristics table. The recommended conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. The suggested conditions are those for which signals will propagate through the unit without significant distortion. The absolute conditions are those for which the unit will produce some type of output for a given input. When operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. However, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. In other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. Please consult the technical staff at Data Delay Devices if your application has specific high-frequency requirements. Please note that the increment tolerances listed represent a design goal. Although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses.
A4-A0 TAENS ENB TENIS IN TDA OUT
A i-1 TOAX TAIS
Ai
PWIN
TDISH
PWOUT
TDISO
Figure 1: Timing Diagram
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PDU1032H
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER SYMBOL MIN TYP Total Programmable Delay TDT 31 Inherent Delay TD0 5.5 Disable to Output Low Delay TDISO 1.7 Address to Enable Setup Time TAENS 1.0 Address to Input Setup Time TAIS 3.6 Enable to Input Setup Time TENIS 3.6 Output to Address Change TOAX See Text Disable Hold Time TDISH See Text Absolute PERIN 16 Input Period Suggested PERIN 40 Recommended PERIN 200 Absolute PWIN 8 Input Pulse Width Suggested PWIN 20 Recommended PWIN 100 * Greater for dash numbers larger than 5 UNITS TINC ns* ns ns ns ns
% of TDT % of TDT % of TDT % of TDT % of TDT % of TDT
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER DC Supply Voltage Input Pin Voltage Storage Temperature Lead Temperature SYMBOL VEE VIN TSTRG TLEAD MIN -7.0 VEE - 0.3 -55 MAX 0.3 0.3 150 300 UNITS V V C C NOTES
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 75C) PARAMETER High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current SYMBOL VOH VOL VIH VIL IIH IIL MIN -1.020 -1.950 -1.480 475 0.5 TYP MAX -0.735 -1.600 -1.070 UNITS V V V V A A NOTES VIH = MAX,50 to -2V VIL = MIN, 50 to -2V
VIH = MAX VIL = MIN
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DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
PDU1032H
PACKAGE DIMENSIONS
32 31
26 25 24
17
.400 TYP.
12 7 8 9 11 15 16
1.650 TYP.
.020 .320 TYP. MAX. .150 .030 .100 .600 .700 .800 1.000 1.400 1.500 .018 TYP.
.012 TYP. .300 TYP.
.075
PDU1032H-xx (Commercial DIP) PDU1032H-xxM (Military DIP)
.020 TYP.
.040 TYP.
.010.002
24 23 22 21 20 19 18 17 16 15 14 13
.710 .590 .005 MAX.
.882 .005 .007 .005
1
2
3
4
5
6
7
8
9
10 11 12
.090 1.100 1.280.020
.100
.280 MAX.
.050 .010
PDU1032H-xxC4 (Commercial SMD) PDU1032H-xxMC4 (Military SMD)
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DATA DELAY DEVICES, INC.
http://www.datadelay.com
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12/17/97 by ICminer.com
Tel: 973-773-2299 Fax: 973-773-9672 Electronic-Library Service CopyRight 2003
PDU1032H
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC 3oC Supply Voltage (Vcc): -5.0V 0.1V Input Pulse: Standard 10KH ECL levels Source Impedance: 50 Max. Rise/Fall Time: 2.0 ns Max. (measured between 20% and 80%) Pulse Width: PWIN = 1.5 x Total Delay Period: PERIN = 10 x Total Delay OUTPUT: Load: Cload: Threshold: 50 to -2V 5pf 10% (VOH + VOL) / 2 (Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
REF PULSE GENERATOR OUT TRIG IN DEVICE UNDER TEST (DUT) OUT IN TRIG OSCILLOSCOPE
ADDRESS SELECT
Test Setup
PERIN PWIN TRISE INPUT SIGNAL
80% 50% 20%
TFALL VIH
80% 50% 20%
VIL TFALL
TRISE OUTPUT SIGNAL VOH
50%
50%
VOL
Timing Diagram For Testing
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DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
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